This application claims the priority of Korean Patent Application No. 2003-12041, filed on Feb. 26, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention generally relates to a semiconductor circuit, and more particularly, to a sense amplifying circuit for detecting and amplifying differential signals with minutely different levels. The present invention also generally relates to a bit comparator employing such a sense amplifying circuit.
2. Description of the Related Art
General sense amplifying circuits are capable of synchronizing two differential signals with minutely different levels with a clock signal, sensing the synchronization signal, amplifying the sensed signal, and outputting the amplified signal.
FIG. 1 illustrates a conventional circuit diagram of a general amplifying circuit. The operation of a sense amplifying circuit 100 will be described with reference to FIG. 1. As is illustrated, two input signals INH and INL with minutely different levels may be applied to the sense amplifying circuit 100. In this case, the input signal INH has a higher voltage level than the input signal INL.
If a clock signal CLK is at a low level, precharge transistors PMP1 and PMP2 precharge first and second nodes N1 and N2, respectively, and NMOS transistors LMN1, LMN2, LM3, and LM4 are turned on.
If the clock signal CLK is transited to a high level, the sense amplifying circuit 100 starts a sensing operation with a switch transistor SWMN turned on. Although the precharge transistors PMP1 and PMP2 are turned on, latch transistors LMP1 and LMP2 keep the first and second nodes N1 and N2 precharged.
Since an NMOS transistor SMN1 receiving the input signal INH allows a larger amount of current to flow than an NMOS transistor SMN2 receiving the input signal INL, a voltage level of the first node N1 is lower than a voltage level of the second node N2.
In other words, the first node N1 is at a low level, and the second node N2 is at a high level. Inverters I1 and I2 invert and output the voltage levels of the first and second nodes N1 and N2.
Accordingly, an output signal OUTH is output as a high level, and an output signal OUTL is output as a low level. As a result, there is an even larger difference between the voltage levels of the output signals OUTH and OUTL.
However, if a sense amplifying circuit should select and amplify one pair of differential signals from two pairs of differential signals, because the two pairs of differential signals are low-noise signals having a small swing, a general sense amplifying circuit generally must amplify both pairs and then select one pair. This may create a logic burden on a rear end of the sense amplifying circuit.
FIG. 2 illustrates a conventional circuit diagram of a general bit comparator.
The general bit comparator compares a tag value with address data input to a contents address memory (CAM) in a cache memory. The CAM is capable of storing data input from an external source, and comparing the stored data with address data input from an external source to determine whether the stored data coincides with the address data. The data stored in the CAM is generally called a tag, and the bit comparator compares the tag with input address data.
The operation of the general bit comparator will be explained with reference to FIG. 2. A data maintainer 230 has a latch structure in which input nodes of inverters ID1 and ID2 are connected to output nodes of the inverters ID1 and ID2, and receive and store data DATA and inverted data INDATA from a pair of bit lines BL and BLB via transistors CMN1 and CMN2 controlled by a word line WL. This value is a tag.
Assuming that the data DATA has a low level, the inverted data INDATA has a high level, and address data INH and INL that do not coincide with the data DATA and inverted data INDATA are input. In other words, the address data INH is at a high level, and the address data INL is at a low level.
The address data INH and INL is input to a driver 220 via a sense amplifying circuit 210 which operates in synchronicity with a clock signal CLK. The sense amplifying circuit 210 generally has the same structure as the general sense amplifying circuit 100 shown in FIG. 1, and the address data INH and INL is amplified through the sense amplifying circuit 210 and the driver 220.
When the data DATA and the inverted data INDATA is applied to transmission gates TG1 and TG2, respectively, the transmission gate TG1 is turned on, and the transmission gate TG2 is turned off. The address data INH with the high level is output as a match signal MATL via the transmission gate TG1. The address data INL with the low level is not output because the transmission gate TG2 is turned off.
Outputting the match signal MATL at a high level indicates that the address data INH and INL input to a bit comparator 200 may each have a different level from the data DATA and the inverted data INDATA. Outputting the match signal MATL at a low level indicates that the address data INH and INL input to the bit comparator 200 each have the same level as the data DATA and the inverted data INDATA.
A general bit comparator normally generates a match signal by amplifying input address data through a sense amplifying circuit and a driver, and comparing the input address data with stored data. As a result, a significant time is taken from the input of the address data to the output of the match signal. This is problematic in a cache memory which is required to operate at a high speed.